1. Field
Embodiments of the invention relate to a signal transmission circuit with a simple configuration wherein a multiple of signals can be level shifted and reliably transmitted between a high side circuit and low side circuit of differing operating reference voltages.
2. Description of Related Art
A power converter, including two power semiconductor elements Q1 and Q2, connected in a totem pole configuration to form a half-bridge circuit, that switch direct current voltage by alternately carrying out on/off operations, is known as a power converter that drives an alternating current load. For example, a high voltage integrated circuit (HVIC) including a high side driver (high side circuit), which carries out switching the drive of the upper arm side power semiconductor element Q1, and a low side driver (low side circuit), which carries out switching the drive of the lower arm side power semiconductor element Q2, is used as a drive circuit of this kind of power converter.
Herein, the high side circuit is configured to operate by receiving a predetermined power supply voltage VB (>VS), with a midpoint voltage (first voltage) VS of the half-bridge circuit as a reference potential. Also, the low side circuit is configured to operate by receiving a predetermined power supply voltage VCC (>GND), with a ground voltage (second voltage) GND of the half-bridge circuit lower than the midpoint voltage (first voltage) VS as a reference potential.
Herein, a protective circuit that protects the power semiconductor elements Q1 and Q2 by detecting an abnormality such as overcurrent or overheat in the power semiconductor elements Q1 and Q2, and a signal output circuit that transmits an abnormality detection signal to a control circuit portion of the high side circuit and low side circuit, are provided in the high side circuit and low side circuit. However, the high side circuit, as previously described, is configured to operate with the midpoint voltage VS of the half-bridge circuit as a reference potential. Also, the low side circuit is configured to operate with the ground voltage GND as a reference potential. Therefore, in order to transmit an abnormality detection signal, or the like, detected by the high side circuit to the low side circuit, it is necessary to reduce the level of the abnormality detection signal. Also, conversely, when transmitting a signal from the low side circuit to the high side circuit, it is necessary to increase the level of, for example, a control signal or the like.
Level shifter circuits wherein the level of a signal input into the low side circuit is increased and the signal is transmitted to the high side circuit are introduced in, for example, PTL 1 and 2. These level shifter circuits include a two system circuit formed of semiconductor switch elements MN1 and MN2, formed of n-type MOSFETs, connected in series with resistors R1 and R2 respectively and provided in parallel in the low side circuit, as shown in each of FIG. 27 and FIG. 28. Further, the configuration is such that an on-state signal in accordance with a signal to be transmitted from the low side circuit toward the high side circuit is transmitted via the one semiconductor switch element MN1, while an off-state signal is transmitted via the other semiconductor switch element MN2, and a latch circuit provided in the high side circuit is set and reset using these signals.
Herein, when transmitting a signal from the high side circuit toward the low side circuit, an on-state signal and an off-state signal are transmitted by semiconductor switch elements formed of p-type MOSFETs provided in parallel in the high side circuit being turned on and off. Further, the configuration is such that a latch circuit provided in the low side circuit is set and reset by the on-state signal and the off-state signal. In Japanese Patent Publication JP-A-9-200017 (PTL 1), an RS flip-flop is used as the latch circuit, as shown in FIG. 27. In Japanese Patent Publication JP-A-2011-44770 (PTL 2), a level trigger type of latch circuit configured by a p-type MOSFET and n-type MOSFET being connected in series is used, as shown in FIG. 28.